1. Field of the Invention
The present invention generally relates to a semiconductor package, and more particularly to the stack package that one package consists at least two semiconductor chips stacked therein.
2. Description of the Related Art
Rapid progress in the memory chip has been presented to increase memory capacity. Currently, 128M DRAM is mass-produced, and also the mass-production of 256M DRAM will be available sooner or later.
For increasing memory chip capacity, i.e. high integration, a technology for inserting cells as many as possible into a given area of semiconductor device, is widely known. However, this method requires high technology such as a precise line width and a considerable amount of time for development. Accordingly, a relatively simpler stacking technology to optimize integrity of the semiconductor device has been developed most recently.
The term "stacking" used in semiconductor industry means a technique to double the memory capacity by heaping up at least two semiconductor chips in a vertical direction. According to the stacking technique, a 128M DRAM device can be constituted by two 64M DRAM devices for instance, also a 256M DRAM device can be constituted by two 128M DRAM devices.
Merely an example of a package fabricated according to the typical stacking technique is illustrated in FIG. 1.
As shown in the drawing, an inner lead 21 of a lead frame 2 is attached by means of an adhesive to a semiconductor chip 1 in which a bonding pad is disposed on an upper portion of the semiconductor chip 1. The inner lead 21 is connected to the bonding pad with a metal wire 3. The entire resultant is molded with an epoxy compound 4 such that both ends of the outer lead 22 is exposed therefrom.
On the package as constituted above, another package having the same constitution as above is stacked. That is to say, the outer lead 22 of the package in the upper position is in contact with a midway portion of the lead frame 2 in the lower position thereby electrically connecting each other.
However, there is a drawback in the general stack package that total thickness of the package is too thick. Further, since an electrical signal should pass the lead frame of the lower package through the outer lead of the upper package, there is another drawback that the electrical signal path is too long. Especially, bad connections are occurred frequently due to bad soldering since leads of both upper and lower packages are joined with each other by soldering.
A conventional stack package to solve foregoing problems is illustrated in FIG. 2.
As shown in the drawing, the respective back sides of upper and lower semiconductor chips 1b,1a are attached with an adhesive. An inner lead 21b of an upper lead frame 2b is attached on the top surface of the upper semiconductor chip 1b, thereby electrically connecting the inner lead 21b and bonding pad with a metal wire 3b. Further, the inner lead 21a of a lower lead frame 2a is attached on the bottom surface of the lower semiconductor chips 1a thereby electrically connecting the inner lead 21a and the bonding pad with a metal wire 3a. An outer lead 22b of upper lead frame 2b is bonded at a midway portion of the lower lead frame 2a and the entire resultant is molded with an epoxy compound 4 such that an outer lead 22a of the lower lead frame 2a is exposed therefrom.
This type of stack package often shortens the electrical signal path. However, even one between two semiconductor chips has bad function, then two semiconductor chips are all abandoned since a connecting portion between upper and lower lead frames 2a,2b is located within the epoxy compound 4.